Qualcomm and Amazon Announce AI Data-Center Deal


TL;DR

  • Deal: Qualcomm and Amazon agreed to develop customized AI-inference silicon and optical links supporting speeds up to 1.6 terabits per second.
  • Warrant: An Amazon affiliate may buy up to 25 million Qualcomm shares as commercial milestones and purchases vest tranches.
  • Limits: Neither company disclosed product architecture, quantities, delivery dates, measured performance or ordinary financial terms.

Qualcomm and Amazon announced a multi-generation data-center collaboration on September 8 that covers customized silicon for AI inference and optical links reaching up to 1.6 terabits per second. A separate purchase-linked warrant, already partly vested on initial purchase commitments, gives the engineering plan unusual commercial weight even though neither company disclosed products, delivery dates or ordinary financial terms.

The agreement puts Qualcomm’s data-center expansion inside a major cloud operator that already builds its own processors and AI accelerators. It also joins two complementary constraints: chips must run trained AI models, while high-speed connections must move data among the machines doing that work. The warrant makes Amazon’s future purchases relevant to both Qualcomm’s sales ambitions and possible future Amazon ownership of Qualcomm shares.

What the Two Technical Tracks Cover

 Inference is the stage at which a trained AI model processes new input and generates an answer or prediction. Customized silicon means chips tailored to a customer’s workloads and systems.

The companies did not say whether the resulting designs will be CPUs, GPUs or another type of accelerator. A CPU handles a broad range of general-purpose and control work. GPUs perform many calculations in parallel, which makes them widely used for AI training and inference. Specialized accelerators can take on narrower AI tasks, and all three types can operate in the same data center.

Qualcomm will contribute serializer-deserializer, or SerDes, technology that turns parallel chip data into high-speed serial streams and back again, plus optical digital signal processors that condition those streams for transmission over light. The announced ceiling of 1.6T refers to roughly 1.6 terabits of data per second for a link or transceiver class.