TL;DR
- New Platform: Taiwan launched CoCoB, a substrate-less chip packaging research platform that eliminates costly layers used in commercial packaging technologies.
- Target Users: The open-access platform enables academic institutions and startups to prototype advanced chip designs without industrial-scale budgets.
- Early Adoption: Sixteen research teams from Taiwan and abroad have already joined the initiative announced January 13.
- Industry Context: The platform arrives as commercial CoWoS capacity remains constrained, though it serves research needs rather than production volumes.
At a Taipei press event on January 13, researchers from Taiwan’s semiconductor institutes unveiled a platform designed to give academics and startups something they’ve long lacked: access to advanced chip packaging capabilities without industrial-scale budgets.
The nation’s National Institutes of Applied Research launched CoCoB, a substrate-less packaging platform that lets research teams prototype AI chip designs using techniques previously available only through commercial foundries. While the platform won’t solve the industry’s commercial capacity constraints, it opens a door for innovations that might otherwise never leave the lab.
The Innovation
What makes this platform different comes down to architecture. Taiwan Semiconductor Research Institute presented Chip-on-Chip-on-Board (CoCoB), an architecture that directly connects interposer chips to circuit boards.
By eliminating the costly substrate layer that sits between those components in conventional packaging, CoCoB shortens signal transmission paths while cutting both material costs and process complexity.
Promo
The open R&D platform targets academic institutions and startups seeking high-flexibility, low-cost heterogeneous integration experiments. Already, 16 professor-led research teams from Taiwan and abroad have joined the project.
That said, achieving direct board connection presented technical hurdles. TSRI Deputy Director General Juang Ying-zong explained the challenge through a vivid analogy: “placing a large sheet of tempered glass onto a pebble-covered ground while ensuring every single contact point is precisely connected.”
TSRI’s solution involved implementing flowable interface material beneath each micro-solder ball to ensure reliable bonding across irregular surfaces.
Technical Context
To grasp why this matters, consider what CoCoB simplifies. TSMC introduced CoWoS (Chip-on-Wafer-on-Substrate) in 2012, using interposer wafers and substrates to achieve high-density integration of computing chips and high bandwidth memory.
CoWoS has three variants: CoWoS-S uses silicon interposers for HBM and GPU integration, CoWoS-R employs redistribution layers for cost-sensitive applications, and CoWoS-L combines hybrid silicon with RDL for larger packages supporting up to 12 HBM stacks.
While effective for high-volume production, those substrate layers create barriers for researchers: high costs, complex processes, and minimum order quantities that put the technology out of reach for academic labs. CoCoB’s substrate-less approach trades some of CoWoS’s production-scale optimization for accessibility, enabling research teams to experiment with advanced packaging concepts at a fraction of the cost.
The Commercial Capacity Problem
CoCoB arrives amid a broader industry challenge, though it addresses a different problem than the one making headlines. TSMC’s long-standing production capacity bottleneck for CoWoS has become a major obstacle for commercial chip development.
Demand for 3D wafer-level packaging from Nvidia and a handful of companies making AI chips has exceeded TSMC’s ability to meet demand since last year. CoWoS capacity is booked out by flagship AI players such as Nvidia, AMD, and Google.
TSMC is aggressively expanding capacity from 13,000 wafers per month at the end of 2023 to a planned 70,000-80,000 by the end of 2025, with a target of over 100,000 in 2026. Yet demand keeps growing alongside chip complexity. New architectures like Nvidia Blackwell consume 3.3× reticle space compared to previous generations, and upcoming Rubin is expected to require 4.0×, putting additional strain on available capacity.
This commercial capacity crunch affects companies seeking high-volume production. CoCoB operates in a different space entirely: it serves researchers who need dozens or hundreds of prototype units to validate novel architectures, not the millions of units that commercial customers require.
Why Packaging Matters
The strategic importance of advanced packaging explains why even a research platform like CoCoB has significance for the industry’s future.
The market reflects this strategic importance. Advanced packaging accounts for about 8% of the total semiconductor market today and is projected to double by 2030 to more than $96 billion. AI applications account for 25% of the total advanced packaging market already, and this is expected to grow at around 20% per year through the next decade.
Given packaging’s growing importance, providing researchers early access to experiment with advanced techniques could accelerate the development of next-generation architectures – even if those innovations ultimately require commercial foundries to reach production scale.
Bridging Research and Production
CoCoB’s open platform approach specifically targets those who cannot access commercial foundry services: academic institutions and startups conducting heterogeneous integration experiments. The 16 research teams already participating can now validate chip architectures that might otherwise remain theoretical.
The platform fills a gap in the innovation pipeline. Commercial foundries like TSMC optimize for high-volume customers who can commit to large production runs. Researchers exploring novel architectures typically need small batches – dozens or hundreds of units – to prove concepts before seeking manufacturing partners. Without platforms like CoCoB, promising ideas may never progress past simulation.
Wu Cheng-wen’s dual role as NIAR chairperson and minister of the National Science and Technology Council positions the initiative as both a research platform and a national technology development effort. Juang Ying-zong, serving as TSRI Deputy Director General, brings the technical leadership needed to tackle the bonding challenges inherent in substrate-less architectures.
Commercial Alternatives
For companies seeking production-scale solutions to the capacity bottleneck, several alternatives are emerging. CoPoS (Chip-on-Panel-on-Substrate) replaces silicon interposer with panel-scale RDL (600×600 mm+), achieving 95%+ panel utilization versus 85% in CoWoS. CoPoS offers 20-30% lower cost per unit area and supports 10-12 HBM4 stacks for AI servers. CoWoP (Chip-on-Wafer-on-PCB) directly bonds silicon interposer to PCB without ABF substrate, reducing cost by 40-50% while providing shorter signal paths for higher-speed interfaces.
Where TSMC optimized CoWoS for high-volume manufacturing, these alternatives optimize for different constraints: CoPoS for cost efficiency at scale, CoWoP for thermal performance. CoCoB, by contrast, optimizes for research accessibility rather than production volume.
Intel Foundry presents another option for commercial customers. The company has excess advanced packaging capacity and is welcoming TSMC customers to transfer their designs directly from TSMC’s CoWoS to Intel’s Foveros.
Second-tier ASIC vendors and major U.S. chipmakers are now exploring Intel’s EMIB and Foveros as alternative back-end options. Intel uses 3D stacking with active base die featuring TSVs, achieving 36 µm interconnect pitch.
While Intel is expanding capacity for Foveros Direct 3D at its New Mexico site and plans to ramp up Foveros output by 30%, thermal constraints from vertical stacking limit some applications compared to TSMC’s lateral approach.
Future Outlook
TSMC continues advancing its commercial offerings. CoPoS is positioned as TSMC’s successor to CoWoS, with first experimental line at subsidiary Caiyu launching in 2026. A mass-production factory is confirmed for Chiayi AP7, with a goal of achieving large-scale mass production between the end of 2028 and 2029. NVIDIA will be first customer.
Meanwhile, TSMC is expanding CoWoS capabilities to support larger interposers, moving from today’s 3.5× reticle size to 5×, 9×, and beyond. The company aims to mass-produce 9.5 reticle size CoWoS by 2027, enabling packages with 12 or more HBM stacks.
For the 16 research teams now working with CoCoB, and the academic institutions and startups waiting to join them, the platform offers something different: a pathway to experiment with advanced packaging techniques without requiring commercial-scale commitments.
The platform’s impact will depend on whether academic prototypes can demonstrate innovations compelling enough to attract manufacturing partners for eventual production. Taiwan’s January 13 launch reflects a recognition that breakthrough chip architectures often emerge from research labs – and those labs need access to advanced packaging tools to move from concept to prototype.
What happens after prototyping remains a separate challenge, one that commercial foundries and their expanding capacity will ultimately need to address.